.syntax unified

.equ L152,1
.include "../Core/src/regs.s"

.global mainasm

mainasm:



main:
	ldr		R0,=hadc
	bl		HAL_ADC_Start
	ldr 	R4,=GPIOC
	mov		R5,#10			//Geschwindigkeit
	ldr		R6,=GPIOA
	ldr		R8,=TIM2
	mov		R0,#1
	str		R0,[R8,CR1]
	str		R0,[R8,CNT]
schleife:
	//mov		R0,#0
	//str		R0,[R8,CR1]
	//str		R0,[R8,CNT]
	ldr		R0,=hadc
	bl		HAL_ADC_GetValue
	strh	R0,[R8,ARR]
	mov		R5,R0
	//mov		R0,#1
	//str		R0,[R8,CR1]

	ldr		R0,[R6,ODR]
	tst		R0,Bit5
//	beq		links

	mov		R0,#0b0011		//Schritt 0
	strb 	R0,[R4,ODR]		//ausgeben
	//lsr		R0,R5,8			//Wartezeit=Geschwindigkeit
	//bl		HAL_Delay			//warten
warte1:
	ldr		R0,[R8,SR]
	tst		R0,Bit0
	beq		warte1
	mov		R0,#0
	strb	R0,[R8,SR]

	mov		R0,#0b0110
	strb 	R0,[R4,ODR]
//	lsr		R0,R5,8
//	bl		HAL_Delay
warte2:
	ldr		R0,[R8,SR]
	tst		R0,Bit0
	beq		warte2
	mov		R0,#0
	strb	R0,[R8,SR]

	mov		R0,#0b1100
	strb 	R0,[R4,ODR]
//	lsr		R0,R5,8
//	bl		HAL_Delay
warte3:
	ldr		R0,[R8,SR]
	tst		R0,Bit0
	beq		warte3
	mov		R0,#0
	strb	R0,[R8,SR]

	mov		R0,#0b1001
	strb 	R0,[R4,ODR]
//	lsr		R0,R5,8
//	bl		HAL_Delay
warte4:
	ldr		R0,[R8,SR]
	tst		R0,Bit0
	beq		warte4
	mov		R0,#0
	strb	R0,[R8,SR]

	b 		schleife

links:
	mov		R0,#0b0011		//Schritt 0
	strb 	R0,[R4,ODR]		//ausgeben
	lsr		R0,R5,8			//Wartezeit=Geschwindigkeit
	bl		HAL_Delay			//warten
	mov		R0,#0b1001
	strb 	R0,[R4,ODR]
	lsr		R0,R5,8
	bl		HAL_Delay
	mov		R0,#0b1100
	strb 	R0,[R4,ODR]
	lsr		R0,R5,8
	bl		HAL_Delay
	mov		R0,#0b0110
	strb 	R0,[R4,ODR]
	lsr		R0,R5,8
	bl		HAL_Delay

	b 		schleife

.global HAL_GPIO_EXTI_Callback
HAL_GPIO_EXTI_Callback:
	ldr		R0,[R6,ODR]
	eor		R0,Bit5
	strb	R0,[R6,ODR]
	bx		lr


.end
