.syntax unified
.equ L152,1
.include "../Core/src/regs.s"
.global mainasm
mainasm:



main:
	ldr		R2,=GPIOC
schleife:
/*
	mov		R0,#Bit0
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s
*/
	mov		R0,#Bit1
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit2
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit3
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit4
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit5
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit6
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit7
	strb	R0,[R2,BSR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit0
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit1
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit2
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit3
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit4
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit5
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit6
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s

	mov		R0,#Bit7
	strb	R0,[R2,BRR]	//Bit Set Register
	bl		warte1s



	b		schleife

warte1s:
	ldr		R0,=32000000/5
	mov		R1,#1
w1:
	subs	R0,R1
	bne		w1
	bx		lr

.end
